CPC G06F 3/0619 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0679 (2013.01); G11C 16/3404 (2013.01)] | 20 Claims |
1. A memory device comprising:
a memory cell string including first memory cells included in a first channel area formed vertically on a substrate, second memory cells included in a second channel area positioned on the first channel area, and dummy memory cells included in the second channel area and connected between the first memory cells and the second memory cells;
a peripheral circuit configured to perform a program operation of storing data in the first and second memory cells; and
a program operation controller configured to control the peripheral circuit to sequentially apply a first pass voltage and a second pass voltage less than the first pass voltage to a dummy word line connected to the dummy memory cells during the program operation, and then apply a program voltage to a selected word line among a plurality of word lines connected to the first and second memory cells.
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