| CPC G06F 3/0619 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
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1. A semiconductor memory device, comprising:
a memory cell array having a plurality of rows of memory cells therein; and
a row hammer handler configured to generate a refresh address when performing a refresh operation on the plurality rows of memory cells, said row hammer handler comprising:
a weight distributor configured to: receive a plurality of row addresses, assign a weight to each of the plurality of row addresses thus received, and to generate weight data corresponding to each of the plurality of row addresses;
an aggress address generator configured to determine an aggress address of a row of memory cells based on the weight data; and
a refresh address generator configured to receive the aggress address and to generate the refresh address, which includes address information of a memory cell row adjacent the aggress address;
wherein the weight assigned to each of the plurality of row addresses thus received has a value that varies relative to the order in which it is received; and
wherein the weight data associated with each of the plurality of row addresses is a function of at least one weight associated with its order of receipt and a frequency of its receipt over a predetermined time interval.
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