| CPC G06F 3/0613 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0683 (2013.01)] | 20 Claims |
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1. An accelerator module, comprising:
a plurality of memories; and
a controller configured to control operations of the plurality of memories, and
wherein the controller includes:
a plurality of memory controllers connected to the plurality of memories, respectively, the plurality of memory controllers and the plurality of memories forming a plurality of memory sub-channels;
a plurality of processing units connected to the plurality of memory controllers, respectively, and configured to perform computational operations on a plurality of data stored in or read from the plurality of memories; and
a managing circuit connected to the plurality of processing units, and configured to redistribute tasks performed by the plurality of processing units or change connections between the plurality of memory controllers and the plurality of processing units in response to at least one of the plurality of memory sub-channels and/or one or more of the plurality of processing units being in a heavy-workload state.
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