CPC G06F 3/061 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] | 18 Claims |
1. A memory controller comprising:
a latency monitoring component configured to generate information about a number of occurrences of over-latency exceeding a preset reference latency among latencies each indicating a time amount required from a time point at which first command is received from an external device to a time point at which a completion response to the first command is transmitted to the external device during a first period; and
a completion response controller configured to determine a first target latency based on the information about the number of occurrences of over-latency, and provide, during a second period following the first period, the external device with a completion response to a second command provided from the external device after the first target latency has elapsed,
wherein the information is determined using an average latency of the latencies during the first period and a maximum latency which has a largest latency among the latencies.
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