| CPC G06F 21/566 (2013.01) [G06F 9/30029 (2013.01); G06F 21/554 (2013.01)] | 16 Claims |
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1. A method of concealing a logic state in a target logic circuit against an optical probing, wherein the target logic circuit is coupled to at least one input signal, the method comprising:
forming one or more concealing logic circuits in close optical proximity to the target logic circuit, wherein:
the target logic circuit comprises a target transistor, the target transistor is one of NMOS transistor or PMOS transistor;
the one or more concealing logic circuits comprise a concealing transistor, the concealing transistor is a same type transistor as the target transistor;
the target transistor is coupled to a first input signal of the at least one input signal, wherein in response to the first input signal, the target transistor operates in either a saturation region or a cutoff region; and
the concealing transistor is coupled to a complement of the first input signal, wherein, in response to the complement of the first input signal, the concealing transistor operates in an opposite region of operation region of the target transistor.
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