| CPC G06F 21/53 (2013.01) [G06F 9/45558 (2013.01); G06F 2009/45579 (2013.01); G06F 2009/45587 (2013.01)] | 20 Claims |
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1. A system on a chip (SoC), comprising:
a first hardware processing element to execute a trusted operating system (OS) that is assigned to a first level in a hierarchy;
a second hardware processing element to execute a first hypervisor or OS that is assigned to a second level in the hierarchy;
a third hardware processing element to execute a second hypervisor or OS that is assigned to a third level in the hierarchy, wherein the first, second, and third hardware processing elements are different from each other;
memory where a first portion of the memory is assigned to the first level, a second portion of the memory is assigned to the second level, and a third portion of the memory is assigned to the third level, wherein the trusted OS is authorized to manage the first, second, and third portions of the memory, the first hypervisor or OS is authorized to manage the second and third portions of the memory but not the first portion of the memory, and the second hypervisor or OS is authorized to manage only the third portion of the memory; and
an interconnect that communicatively couples the respective hardware processing elements to the memory and prevents resources of the second and third hardware processing elements from accessing registers of the interconnect configured by resources of the first hardware processing element.
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