CPC G06F 16/2379 (2019.01) [G06F 16/24568 (2019.01)] | 20 Claims |
1. A system comprising:
at least one hardware processor; and
a memory storing instructions that cause the at least one hardware processor to perform operations comprising:
receiving, at a first execution node, a broadcast of an execution request for a first transaction, the broadcast of the execution request being broadcasted by a leader node for the first transaction, the execution request including an execution command corresponding to the execution request and a first execution timestamp, the execution command including a plurality of operations to execute the execution request;
determining, by the first execution node, that the first execution node is assigned to execute at least a portion of the execution request in response to receiving the broadcast of the execution request for the first transaction, the first execution node being assigned to execute the execution command corresponding to the execution request;
blocking receipt of a second execution timestamp associated with a second transaction;
executing, by the first execution node, at least a first operation of the execution command corresponding to the execution request based on the first execution timestamp; and
unblocking receipt of the second execution timestamp associated with the second transaction.
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