| CPC G06F 16/1724 (2019.01) [G06F 3/0608 (2013.01); G06F 3/0619 (2013.01); G06F 3/064 (2013.01); G06F 3/0649 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G06F 16/164 (2019.01); G06F 16/172 (2019.01); G06F 16/1727 (2019.01); G06F 16/174 (2019.01)] | 20 Claims |
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1. An apparatus, comprising:
a first memory device;
a second memory device, wherein the second memory device is a buffer; and
a controller, coupled to the first memory device and the second memory device, configured to:
receive and write data to the second memory device at a first rate;
set a first defrag level for the first memory device, wherein the first defrag level is associated with transferring data from the second memory device to the first memory device and performing defrag operations on the first memory device at a second rate;
transfer a first portion of the data from the second memory device to the first memory device and performing a first number of defrag operations on the first memory device at the second rate based on the first defrag level;
set a second defrag level for the first memory device in response to a determination that the second memory device is full due to writing the data to the second memory device at the first rate while writing the first portion of the data to the first memory device and performing the first number of defrag operations on the first memory device at the second rate according to the first defrag level such that the first rate is greater than the second rate, wherein the second defrag level is associated with transferring data from the second memory device to the first memory device and performing defrag operations on the first memory device at a third rate;
and
transfer a second portion of the data from the second memory device to the first memory device and perform a second number of defrag operations on the first memory device at the third rate based on the second defrag level, wherein an amount of time that the first memory device is performing the second number of defrag operations on the first memory device is less than an amount of time that the first memory device is performing the first number of defrag operations on the first memory device.
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