US 12,235,792 B2
Apparatus and method for temperature-constrained frequency control and scheduling
Jianwei Dai, Portland, OR (US); Somvir Singh Dahiya, Hillsboro, OR (US); Mahesh Kumar P, Bangalore (IN); Stephen H. Gunther, Beaverton, OR (US); Sapumal Wijeratne, Portland, OR (US); and Mark Gallina, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 30, 2023, as Appl. No. 18/128,852.
Prior Publication US 2024/0330234 A1, Oct. 3, 2024
Int. Cl. G06F 9/50 (2006.01); G06F 1/324 (2019.01); G06F 9/48 (2006.01); G06F 15/78 (2006.01)
CPC G06F 15/7814 (2013.01) [G06F 1/324 (2013.01); G06F 9/4893 (2013.01); G06F 9/5044 (2013.01); G06F 9/505 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A processor comprising:
a plurality of cores;
power management circuitry to control a frequency of each core of the plurality of cores based, at least in part, on a temperature associated with one or more cores of the plurality of cores, the power management circuitry comprising:
a temperature limit-driven frequency controller to determine a first frequency limit value based on a temperature of a corresponding core reaching a first threshold;
frequency prediction hardware logic to predict a temperature-constrained frequency of the corresponding core based on the first frequency limit value and an initial frequency limit value; and
performance determination hardware logic to determine a new performance value for the corresponding core based on the temperature-constrained frequency, the new performance value to be provided to a scheduler.