US 12,235,791 B2
Loop driven region based frontend translation control for performant and secure data-space guided micro-sequencing
Kameswar Subramaniam, Austin, TX (US); and Christopher Russell, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 23, 2021, as Appl. No. 17/409,090.
Prior Publication US 2023/0056699 A1, Feb. 23, 2023
Int. Cl. G06F 9/38 (2018.01); G06F 9/32 (2018.01); G06F 15/78 (2006.01)
CPC G06F 15/78 (2013.01) [G06F 9/325 (2013.01); G06F 9/3818 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
Data-space Translation Logic (DTL) circuitry to receive a static input and a dynamic input and to generate one or more outputs based at least in part on the static input and the dynamic input; and
a frontend counter to generate a count value for the dynamic input based at least in part on an incremented/decremented counter value and a next counter value from the DTL circuitry,
wherein the DTL circuitry is capable to receive a new dynamic input prior to consumption of the one or more outputs.