a hardware processor;

a memory device operatively coupled to a serial peripheral interface (SPI) chip and the hardware processor;

a power management unit (PMU) to provide power to the hardware processor and memory device;

the SPI chip to interface the hardware processor executing plural stages of boot firmware modules during a boot process of the information handling system to allocated, reserved portions of the memory device for each stage of boot module executed in pre-boot, boot, and runtime phases;

the hardware processor, via the SPI chip, executes an original equipment manufacturer (OEM)-defined agnostic memory allocation firmware module to generate a virtual interface for a customized set of allocated, reserved portions of the memory device for the plural stages of the boot modules; and

the hardware processor executing the OEM defined agnostic memory allocation firmware to redefine the virtual interface for each allocated reserved portion of the memory device at each of the plural stages of the boot modules that are executed from pre-boot, through boot, and to runtime to adjust reserved portions of the memory for at least one of those boot modules executed by the hardware processor.