| CPC G06F 13/4282 (2013.01) [G06Q 20/06 (2013.01)] | 20 Claims |
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1. A compute integrated circuit for a cryptocurrency miner, the compute integrated circuit comprising:
an interface to a shared bus;
a register file comprising a plurality of registers and a programmable register set configuration, wherein the programmable register set configuration specifies a register of the register file and a latency that specifies a beginning for a slot of the shared bus in which to return a value from the specified register on the shared bus; and
a manager configured to:
receive a multicast read command via the interface to the shared bus;
identify, based on the programmable register set configuration, the specified register of the register file to be read by the multicast read command and the slot in which to return the value from the specified register; and
return, via the interface to the shared bus, the value from the specified register in the slot specified by the latency of the programmable register set configuration.
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