| CPC G06F 13/4027 (2013.01) [G06F 12/0246 (2013.01); G06F 13/1694 (2013.01); G06F 13/28 (2013.01); G06F 13/4022 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); G06F 2212/7201 (2013.01)] | 20 Claims |

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1. A computer system comprising:
a first board having an I/O controller hub including a main communication chipset;
a common bus; and
a plurality of Sibling boards coupled to said first board by said common bus, each of the Sibling boards comprising,
a memory operative to host a Sibling operating system, and
at least one graphics processing unit (GPU) coupled to said memory, said Sibling board configured without a Sibling chipset;
wherein at least one of the plurality of Sibling boards functions as a processing unit of said first board, and at least one of said Sibling boards is coupled to and shares said I/O controller hub.
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