	US 12,235,782 B2
	NoC routing in a multi-chip device
Aman Gupta, Sunnyvale, CA (US); Krishnan Srinivasan, San Jose, CA (US); Ahmad R. Ansari, San Jose, CA (US); and Sagheer Ahmad, Cupertino, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Dec. 21, 2022, as Appl. No. 18/086,531.
Prior Publication US 2024/0211422 A1, Jun. 27, 2024
Int. Cl. G06F 13/40 (2006.01); G06F 12/1009 (2016.01)

CPC G06F 13/4022 (2013.01) [G06F 12/1009 (2013.01); G06F 13/4036 (2013.01); G06F 13/4068 (2013.01); G06F 2213/0038 (2013.01)]

19 Claims

1. A multi-chip device, comprising:

a first integrated circuit (IC) comprising a first network on a chip (NoC); and

a second IC comprising a second NoC, wherein the first and second NoCs are communicatively coupled,

wherein, when transmitting traffic from the first NoC to a local destination coupled to the second NoC in the second IC, the traffic is first routed via the first and second NoCs to address translation circuitry in the second IC, and wherein the address translation circuitry is configured to perform an address translation to identify a destination ID for the local destination, add the destination ID into the traffic, and reinsert the traffic into the second NoC to reach the local destination.

9. A method for routing traffic between a first integrated circuit (IC) and a second IC in a multi-chip device, comprising:

routing traffic from a first ingress logic block coupled to a first network on chip (NoC) in the first IC to address translation circuitry coupled to a second NoC in the second IC, wherein the traffic is destined to a local destination in the second IC different from the address translation circuitry;

performing, using the address translation circuitry, an address translation to identify a destination ID for the local destination of the traffic on the second IC and add the destination ID into the traffic; and

routing, using the destination ID, the traffic from a second ingress logic block of the second NoC coupled to the address translation circuitry to an egress logic block of the second NoC corresponding to the local destination.

16. A multi-chip device, comprising:

a first integrated circuit (IC) comprising a first network on a chip (NoC) and first redistribution circuitry; and

a second IC comprising a second NoC and second redistribution circuitry, wherein the first and second NoCs are communicatively coupled,

wherein, when transmitting traffic from the first NoC to a local destination coupled to the second NoC in the second IC, the traffic is first routed via the first NoC to the first redistribution circuitry in the first IC where the traffic exits the first NoC, traverses through an inter-die connection between the first redistribution circuitry and the second redistribution circuitry, is inserted into the second NoC after reaching the second redistribution circuitry, and is forwarded by the second NoC to the local destination, and

wherein the first IC includes a first NoC connection that directly couples the first NoC to a second NoC connection in the second IC coupled to the second NoC, wherein traffic can be transmitted between the first and second NoCs using the inter-die connection and the first and second NoC connections in parallel.