| CPC G06F 13/28 (2013.01) [G06F 9/546 (2013.01)] | 8 Claims |

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1. A time-sensitive network switch, comprising a plurality of multi-core CPUs, is configured to:
in response to receiving data through a physical transmission medium of the time-sensitive network switch, determine a target multi-core CPU in the plurality of multi-core CPUs;
wherein, the target multi-core CPU is configured to:
determine, in response to receiving the data, time-sensitive data and non-time-sensitive data from the data;
determine a first buffer for storing the time-sensitive data and a second buffer for storing the non-time-sensitive data, in a cache resource pool of the time-sensitive network switch; and
identify a priority of the time-sensitive data to allocate the time-sensitive data into a queue at a first port of the time-sensitive network switch to be waiting for transmission;
wherein, the time-sensitive network switch further comprises a DMA controller, configured to output the non-time-sensitive data from a second port of the time-sensitive network switch by the DMA controller;
wherein identifying the priority of the time-sensitive data to allocate the time-sensitive data into the queue at the first port of the time-sensitive network switch to be waiting for transmission comprises:
according to the priority of the time-sensitive data, establishing a function library and a driver set to solve a port queue scheduling scheme for the time-sensitive data; and
according to the port queue scheduling scheme, allocating the time-sensitive data into the queue at the first port of the time-sensitive network switch to be waiting for transmission.
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