US 12,235,773 B2
Two address translations from a single table look-aside buffer read
Joseph Zbiciak, San Jose, CA (US); and Son H. Tran, Murphy, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jan. 26, 2021, as Appl. No. 17/158,095.
Application 17/158,095 is a continuation of application No. 16/251,795, filed on Jan. 18, 2019, granted, now 10,901,913.
Application 16/251,795 is a continuation of application No. 15/384,625, filed on Dec. 20, 2016, abandoned.
Application 15/384,625 is a continuation in part of application No. 14/331,986, filed on Jul. 15, 2014, granted, now 9,606,803, issued on Mar. 28, 2017.
Claims priority of provisional application 61/846,148, filed on Jul. 15, 2013.
Prior Publication US 2021/0149820 A1, May 20, 2021
Int. Cl. G06F 12/1045 (2016.01); G06F 7/24 (2006.01); G06F 7/487 (2006.01); G06F 7/499 (2006.01); G06F 7/53 (2006.01); G06F 7/57 (2006.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 9/345 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 12/0862 (2016.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01); G06F 12/1009 (2016.01); G06F 17/16 (2006.01); H03H 17/06 (2006.01); G06F 15/78 (2006.01)
CPC G06F 12/1045 (2013.01) [G06F 7/24 (2013.01); G06F 7/487 (2013.01); G06F 7/4876 (2013.01); G06F 7/49915 (2013.01); G06F 7/53 (2013.01); G06F 7/57 (2013.01); G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/30018 (2013.01); G06F 9/30021 (2013.01); G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30065 (2013.01); G06F 9/30072 (2013.01); G06F 9/30098 (2013.01); G06F 9/30112 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/3016 (2013.01); G06F 9/32 (2013.01); G06F 9/345 (2013.01); G06F 9/3802 (2013.01); G06F 9/3818 (2013.01); G06F 9/383 (2013.01); G06F 9/3836 (2013.01); G06F 9/3851 (2013.01); G06F 9/3856 (2023.08); G06F 9/3867 (2013.01); G06F 9/3887 (2013.01); G06F 9/48 (2013.01); G06F 11/00 (2013.01); G06F 11/1048 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 12/1009 (2013.01); G06F 17/16 (2013.01); H03H 17/0664 (2013.01); G06F 9/325 (2013.01); G06F 9/381 (2013.01); G06F 9/3822 (2013.01); G06F 11/10 (2013.01); G06F 15/7807 (2013.01); G06F 15/781 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01); G06F 2212/602 (2013.01); G06F 2212/68 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a first virtual address that includes a first portion and a second portion;
receiving a second virtual address that includes a first portion and a second portion;
determining a first physical address for the first virtual address by comparing the first portion of the first virtual address to a set of entries of an address translation table;
determining a second physical address for the second virtual address by comparing the first portion of the second virtual address to the first portion of the first virtual address;
performing an access of a memory using the first physical address; and
performing an access of the memory using the second physical address, wherein:
the memory is a level two cache of a cache hierarchy;
the performing of the access of the memory using the first physical address accesses the level two cache without accessing an intervening level one cache of the cache hierarchy; and
the performing of the access of the memory using the second physical address accesses the level two cache without accessing the intervening level one cache of the cache hierarchy.