US 12,235,772 B2
Vector processor storage
Xavier Aldren Simmons, Cambridge (NZ); Jack Spencer Turpitt, Cambridge (NZ); Rafael John Patrick Shuker, Cambridge (NZ); Tyler Wilson Hale, Cambridge (NZ); Alexander Kingsley St. John, Cambridge (NZ); and Stuart John Inglis, Cambridge (NZ)
Assigned to Daedalus Cloud LLC, Croton-on-Hudson, NY (US)
Filed by Daedalus Cloud LLC, Croton-on-Hudson, NY (US)
Filed on Sep. 7, 2023, as Appl. No. 18/463,256.
Application 18/463,256 is a continuation of application No. 17/590,721, filed on Feb. 1, 2022, granted, now 11,782,844.
Application 17/590,721 is a continuation of application No. 16/556,711, filed on Aug. 30, 2019, granted, now 11,263,145, issued on Mar. 1, 2022.
Claims priority of provisional application 62/746,981, filed on Oct. 17, 2018.
Claims priority of provisional application 62/725,703, filed on Aug. 31, 2018.
Claims priority of provisional application 62/725,691, filed on Aug. 31, 2018.
Prior Publication US 2023/0418761 A1, Dec. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 3/06 (2006.01); G06F 9/38 (2018.01); G06F 11/10 (2006.01); G06F 12/02 (2006.01); G06F 12/0815 (2016.01); G06F 12/10 (2016.01); G06F 12/12 (2016.01); G06F 12/14 (2006.01)
CPC G06F 12/10 (2013.01) [G06F 3/0607 (2013.01); G06F 3/065 (2013.01); G06F 9/30036 (2013.01); G06F 9/30123 (2013.01); G06F 9/3877 (2013.01); G06F 11/1004 (2013.01); G06F 11/1088 (2013.01); G06F 12/0246 (2013.01); G06F 12/0815 (2013.01); G06F 12/12 (2013.01); G06F 12/1408 (2013.01); G06F 3/0679 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/657 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method comprising:
receiving, at a vector processor, a request to store data;
performing, by the vector processor, one or more transforms on the data, wherein performing one or more transforms on the data comprises erasure encoding the data to generate n data fragments configured such that any k of the data fragments are usable to regenerate the data, where k is less than n;
instructing, by the vector processor, one or more storage devices to store the data, wherein instructing one or more storage devices to store the data comprises instructing the one or more storage devices to store the data without the mediation of a central processing unit (CPU); and
receiving, by the vector processor, an acknowledgment from the one or more storage devices that m of the data fragments have been stored, in which k≤m<n.