US 12,235,771 B2
Memory system including nonvolatile memory
Shuichi Watanabe, Fujisawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Feb. 27, 2023, as Appl. No. 18/174,745.
Claims priority of application No. 2022-080917 (JP), filed on May 17, 2022.
Prior Publication US 2023/0376422 A1, Nov. 23, 2023
Int. Cl. G06F 12/10 (2016.01)
CPC G06F 12/10 (2013.01) [G06F 2212/1016 (2013.01); G06F 2212/7201 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A memory system connectable to a host, comprising:
a nonvolatile memory; and
a controller electrically connected to the nonvolatile memory and configured to control the nonvolatile memory, wherein
the controller is configured to:
in response to obtaining a first I/O command from one of a plurality of submission queues stored in a memory of the host,
execute a command process of writing or reading data to or from the nonvolatile memory,
execute an address translation process of translating a first virtual address in a virtual address space of the host to a first physical address for accessing the memory of the host, the first virtual address being a virtual address corresponding to a memory location in the memory of the host to which first information is to be transferred, the first information being information for notifying the host of completion of the first I/O command,
in the address translation process, transmit an address translation request to the host, the address translation request being a request for obtaining first address translation information for translating the first virtual address to the first physical address, and
in response to receiving, from the host, a response indicating that obtainment of the first address translation information fails, suspend a first process of fetching an I/O command from one or more first submission queues in the memory of the host among the plurality of submission queues until the first address translation information is obtained, each of the one or more first submission queues being a submission queue associated with a first completion queue in the memory of the host in which a completion response of the first I/O command is to be stored, and, after the first address translation information is obtained, resume the first process.