| CPC G06F 12/10 (2013.01) [G05B 23/0264 (2013.01); G05B 23/0272 (2013.01)] | 18 Claims |
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1. A failure analysis system of a semiconductor device, the failure analysis system comprising:
a tester configured to:
in each of a plurality of inspection processes including an inspection in a pre-process on an undivided wafter, an inspection in post-process after dividing the wafer into a plurality of chips, and an inspection in final process of semiconductor fabrication that occurs before shipment of a fabricated semiconductor product,
perform tests of the semiconductor device including:
a power source test,
a data transfer test that includes transferring data to a chip of the semiconductor device,
a leakage test,
an open test,
an erasing test that includes erasing data from the chip, and
a program test including programming the chip;
output all addresses of fail blocks or fail columns after conducting one of the tests for determination of normal/failure in a block unit or normal/failure in a column unit in the chip; and
identify a fail block or a fail column occurring during the one of the tests on the basis of a difference between fail address information at an end of the one of the tests and fail address information at an end of an immediately previous test of the tests, and
a data management server connected to a tester collection information file in which information output by the tester is stored, the data management server including:
a receiving unit configured to:
receive, from the tester collection information file, normal/failure information in the block unit and the column unit in the chip in each of the plurality of the inspection processes, and
store the received normal/failure information in a memory;
an information adding unit configured to store, in a failure information management table, the normal/failure information in the block unit and the column unit stored in the memory, with an addition of product information, fabricating information including a lot number, a wafer number, and a chip address, process information, and test information, which are common information ranging over the inspection processes; and
an analyzing unit configured to integratively analyze the normal/failure information in the block unit and the column unit ranging over the plurality of the inspection processes on the basis of the information stored in the failure information management table, wherein
the tester identifies the fail block or the fail column newly occurring during the one of the tests by removing the fail address information at the end of the immediately previous test of the tests from the fail address information at the end of the one of the tests, and thereby collects normal/failure information of the block and normal/failure information of the column in the plurality of inspection processes and output the collected normal/failure information of the block and normal/failure information of the column to the tester collection information file, and
wherein the test information includes at least information used for distinguishing between a regular test for determining normal/failure in a fabricating process and a monitor test in which conditions are accelerated in order to grasp a true capability of the semiconductor device, and the analyzing unit is configured to integratively analyze the normal/failure information in the block unit by determining that a block unit that is initially determined to be a failure in a regular test in post-process inspection is automatically determined to be a failure in pre-process inspection.
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