| CPC G06F 12/0891 (2013.01) [G06F 9/3877 (2013.01); G06F 12/0292 (2013.01); G06F 12/0833 (2013.01); G06F 12/0862 (2013.01); G06F 12/126 (2013.01); G06F 2212/1021 (2013.01)] | 20 Claims |
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1. An apparatus, comprising:
one or more processors configured to issue memory requests to access a memory system; and
cache circuitry configured to cache data from the memory system for access by the one or more processors, wherein:
the cache circuitry includes control circuitry configured to:
assign criticality values to cache lines, wherein a given criticality value indicates that the corresponding cache line is non-critical or has one of multiple criticality levels; and
adjust a criticality value of a cache line in response to a criticality event;
to select a victim cache line for replacement, the cache circuitry is configured to:
mask cache lines having one or more upper criticality levels; and
select the victim cache line from among unmasked cache lines based on access-recency data maintained by the cache circuitry separately from the criticality values.
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