US 12,235,767 B2
Memory interface having multiple snoop processors
Martin John Robinson, Leighton Buzzard (GB); and Mark Landers, Hartwell (GB)
Assigned to Imagination Technologies Limited, Kings Langley (GB)
Filed by Imagination Technologies Limited, Kings Langley (GB)
Filed on Aug. 21, 2023, as Appl. No. 18/236,341.
Application 18/236,341 is a continuation of application No. 17/446,133, filed on Aug. 26, 2021, granted, now 11,734,177, issued on Aug. 22, 2023.
Application 17/446,133 is a continuation of application No. 15/922,258, filed on Mar. 15, 2018, granted, now 11,132,299, issued on Sep. 28, 2021.
Claims priority of application No. 1803291 (GB), filed on Feb. 28, 2018.
Prior Publication US 2023/0393983 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0831 (2016.01); G06F 12/0846 (2016.01); G06F 12/10 (2016.01); G06F 12/1018 (2016.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01)
CPC G06F 12/0831 (2013.01) [G06F 12/0833 (2013.01); G06F 12/0846 (2013.01); G06F 12/10 (2013.01); G06F 13/1673 (2013.01); G06F 13/4068 (2013.01); G06F 12/1018 (2013.01); G06F 2212/62 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for interfacing, at a memory interface, between a memory bus and a cache memory comprising a plurality of cache banks, the memory interface comprising a plurality of snoop processors configured to receive snoop requests from the memory bus, each snoop processor being associated with a respective bus interface, and each bus interface being configured to transfer data to one or more cache banks, of the plurality of cache banks, associated with that bus interface, the method comprising:
receiving a snoop request at a respective bus interface associated with the snoop processor;
determining, at the snoop processor, that the snoop request relates to said respective bus interface; and
processing the snoop request at a cache bank associated with said respective bus interface in dependence on that determination.