US 12,235,764 B2
LBAT bulk update
Steven R. Narum, Meridian, ID (US); and Brian Toronyi, Boulder, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 16, 2022, as Appl. No. 17/946,960.
Claims priority of provisional application 63/348,127, filed on Jun. 2, 2022.
Prior Publication US 2023/0393981 A1, Dec. 7, 2023
Int. Cl. G06F 12/10 (2016.01); G06F 12/02 (2006.01); G06F 12/0804 (2016.01); G06F 12/1027 (2016.01)
CPC G06F 12/0804 (2013.01) [G06F 12/0246 (2013.01); G06F 12/1027 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, by a processing device resident on a logical block address translation (LBAT) acceleration component that reads a codeword comprising multiple sequential logical to physical (L2P) data entries within a cache and makes a same change to all of the multiple sequential L2P data entries of the codeword without performing multiple read and write operations, signaling indicative of performance of an operation to update the plurality of L2P data entries, wherein the plurality of L2P data entries correspond to data written to a memory device, and wherein the plurality of L2P data entries have a same offset from an initial physical address corresponding to each of the plurality of L2P data entries; and
performing the operation to write the update to the plurality of L2P data entries of the codeword responsive to receiving the signaling indicative of performance of the operation to update the plurality of L2P data entries.