a plurality of cores;

a shared cache to be shared by the plurality of cores; and

a cache controller to receive a request from a central processing unit (CPU) responsive to execution of one or more instructions, to lock a portion of the shared cache for exclusive use by a specified physical address range, the cache controller including or having access to one or more registers to store a plurality of fields including a first field to store a base address of the physical address range, a second field to store information to be used in combination with the base address to determine if an address is within the physical address range, and a third field to store an indication of one or more ways, the first, second, and third fields to be written responsive to execution of the one or more instructions, wherein the shared cache comprises a level-2 (L2), or last level cache (LLC), wherein based on the first, second, and third fields, the portion of the shared cache is to be locked for use by cache lines associated with the physical address range, the portion based on the indication of the one or more ways, wherein the cache controller is to provide a response to grant the request based at least on an identified region being unlocked, or a response to deny the request to lock the portion of the shared cache based at least on the portion of the identified region being identified as locked, and wherein cache lines stored in the portion of the shared cache are to only be replaced by other cache lines associated with the physical address range.