| CPC G06F 12/06 (2013.01) [G06F 11/10 (2013.01)] | 20 Claims |
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1. A memory system, comprising:
a host system including a memory controller configured to generate a command address signal, said memory controller comprising:
a first bit signal generator configured to generate a data signal as a plurality of data bits;
a second bit signal generator configured to generate a command address bus inversion bit (CABIB) having a high or low logic level that is a function of a number of data bits within the data signal having a predetermined logic level; and
a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the data signal and the CABIB having a high logic level is an even number; and
a storage system configured to write or read data in response to the command address signal received from the host system.
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