a plurality of control transmitter circuits to transmit, to a memory device, control information including first control information associated with a first mode of the memory controller, second control information; associated with a second mode of the memory controller, and third control information associated with a third mode of the memory controller;

a plurality of data receiver circuits to receive data from the memory device; and

a first steering circuit coupled to the plurality of data receiver circuits, the first steering circuit to, based on the first mode, select between concurrently routing data received from the memory device across all of the plurality of data receiver circuits when all of the plurality of data receiver circuits are enabled and to, based on the second mode, employ at least partial deserialization to concurrently route the data received from the memory device from a first subset of the plurality of data receiver circuits when a second subset of the plurality of data receiver circuits are disabled, the first subset and the second subset to be disjoint, the first steering circuit also to, based on the third mode, receive loopback data from the memory device received via at least one of the plurality of data receiver circuits.