an analog-to-digital conversion circuit configured to sample an input signal based on a clock signal and configured to convert the sampled input signal into a digital code;

a skew detection circuit configured to receive the digital code from the analog-to-digital conversion circuit, calculate a first sum of standard deviations for respective levels of the digital code, compare the first sum of the standard deviations with a previously calculated second sum of standard deviations, and select a smaller value from among the first sum and the second sum; and

a compensation circuit configured to compensate for a skew of the clock signal based on the selected smaller value from among the first sum and the second sum.