| CPC G06F 1/10 (2013.01) | 20 Claims |
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1. An integrated circuit (IC) device comprising:
a circuit comprising pipeline stages; and
controller circuitry configured to:
load a static value into each of the pipeline stages based on a change in a clock enable (CE) signal, and
sequentially deactivate each of the pipeline stages after a quantity of cycles of a reference clock signal that occur after the change of the CE signal, wherein the quantity of cycles of the reference clock signal is based on a quantity of the pipeline stages.
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