US 12,235,670 B2
Clock disciplining and synchronizing
Aaron Foo, Singapore (SG)
Assigned to FMAD Engineering (SNG) Pte. Ltd., Singapore (SG)
Filed by FMAD Engineering (SNG) Pte. Ltd., Singapore (SG)
Filed on Feb. 12, 2024, as Appl. No. 18/439,593.
Application 18/439,593 is a continuation of application No. 17/681,194, filed on Feb. 25, 2022, granted, now 11,940,835.
Prior Publication US 2024/0219954 A1, Jul. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/08 (2006.01); G06F 1/14 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a signal indicative of a reference clock, wherein a local time value is increased by a local time increment on ticks of a hardware clock signal generator;
reading the local time value as a current time value;
determining a difference between the current time value and a previous time value that is based on a previous reading of the local time value;
based on the difference, determining an adjustment to the local time increment so that the local time value increases at a rate that is closer to that of the reference clock; and
modifying the local time increment by the adjustment.