| CPC G02F 1/1368 (2013.01) [G02F 1/136209 (2013.01); G02F 1/136227 (2013.01); G02F 1/136295 (2021.01); H01L 27/1244 (2013.01); H01L 27/1288 (2013.01)] | 19 Claims |
|
1. A substrate, comprising:
a base substrate; and
a plurality of sub-pixel structures arranged in an array on the base substrate,
wherein the sub-pixel structure comprises:
a thin film transistor disposed on the base substrate, the thin film transistor comprising a source and a drain;
an insulating layer disposed on a side of the thin film transistor distal from the base substrate, a first via hole being formed in the insulating layer;
a pixel electrode disposed on a side of the insulating layer distal from the base substrate, the pixel electrode being electrically connected to either the source or the drain through the first via hole; and
a filling block disposed at the first via hole,
wherein the thin film transistor further comprises an active layer and a gate line; wherein the active layer is disposed on a side, proximal to the base substrate, of the source and the drain, and the active layer is electrically connected to the source and the drain; and the gate line is disposed on a side of the active layer distal from the base substrate, and an orthographic projection of the gate line on the base substrate is overlapped with an orthographic projection of the active layer on the base substrate; and
wherein an orthographic projection of a center of the first via hole on the base substrate is between orthographic projections of two active lavers adjacent in a first direction on the base substrate, the first direction being parallel to an extension direction of the gate line.
|