	US 12,235,557 B2
	Displaying base plate and manufacturing method thereof, and displaying device
Zhen Zhang, Beijing (CN); Fuqiang Li, Beijing (CN); Zhenyu Zhang, Beijing (CN); Yunping Di, Beijing (CN); Lizhong Wang, Beijing (CN); Zheng Fang, Beijing (CN); Jiahui Han, Beijing (CN); Yawei Wang, Beijing (CN); Chenyang Zhang, Beijing (CN); Chengfu Xu, Beijing (CN); Ce Ning, Beijing (CN); Pengxia Liang, Beijing (CN); Feihu Zhou, Beijing (CN); Xianqin Meng, Beijing (CN); Weiting Peng, Beijing (CN); Qiuli Wang, Beijing (CN); Binbin Tong, Beijing (CN); Rui Huang, Beijing (CN); Tianmin Zhou, Beijing (CN); and Wei Yang, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/765,769
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Jun. 29, 2021, PCT No. PCT/CN2021/103218 § 371(c)(1), (2) Date Mar. 31, 2022, PCT Pub. No. WO2023/272505, PCT Pub. Date Jan. 5, 2023.
Prior Publication US 2024/0103328 A1, Mar. 28, 2024
Int. Cl. G02F 1/1368 (2006.01); G02F 1/1362 (2006.01); H01L 27/12 (2006.01)

CPC G02F 1/1368 (2013.01) [G02F 1/136286 (2013.01); H01L 27/124 (2013.01); H01L 27/1248 (2013.01); H01L 27/1259 (2013.01)]

9 Claims

1. A displaying base plate, wherein the displaying base plate comprises:

a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer comprises a first electrode pattern;

a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and

a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed close to the substrate, an orthographic projection of the second electrode layer on the substrate covers an orthographic projection of the through hole on the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer, and the second planarization layer fills the through hole to planarize the through hole;

an active area and a non-active area, and the active area comprises an opening region and a non-opening region, wherein the non-opening region at least refers to a region where an orthographic projection of a barrier layer on the substrate overlaps with the substrate, the opening region refers to a region where the orthographic projection of the barrier layer on the substrate does not overlap with the substrate;

a first thin-film transistor disposed on one side of the substrate that is closer to the first electrode layer, the first thin-film transistor is located at the active area, the first thin-film transistor comprises a first active layer, a first grid insulating layer, a first grid, a first interlayer dielectric layer and a first source that are disposed in stack, the first active layer is disposed close to the substrate, and the first active layer comprises a drain contacting region, and the drain contacting region is located at the opening region;

orthographic projections of the first grid insulating layer and the first interlayer dielectric layer on the substrate do not intersect or overlap with the opening region;

the drain contacting region is the first electrode pattern; and

the drain contacting region is directly contacted with the substrate.