a first base substrate;

a plurality of gate lines and a plurality of data lines, arranged on a side of the first base substrate, wherein the plurality of gate lines and the plurality of data lines are arranged to be intersected with each other and insulated from each other;

a planarization layer, arranged on a side of the plurality of gate lines and the plurality of data lines away from the first base substrate, and comprising a first via hole;

a supporting structure, arranged on a side of the planarization layer away from the first base substrate and filled into the first via hole, wherein in a direction perpendicular to the first base substrate, a height of the supporting structure is greater than a depth of the first via hole; and

a first light-shielding structure arranged between a layer where the plurality of gate lines are located and the first base substrate;

wherein a surface of a side of the supporting structure away from the first base substrate is a first surface, the first surface is of a curved-surface structure, a vertical height difference range between a maximum distance and a minimum distance between the first surface and the first base substrate is a, and 0<|a|≤1 μm;

orthographic projections of the plurality of gate lines on the first base substrate and orthographic projections of the plurality of data lines on the first base substrate have a plurality of overlapping regions, and at least part of the overlapping regions are respectively located in an orthographic projection of a corresponding first via hole on the first base substrate;

an orthographic projection of the first light-shielding structure on the first base substrate at least covers the orthographic projection of the first via hole outside a corresponding overlapping region on the first base substrate.