wherein the array substrate comprises:

a first substrate, comprising a plurality of sub-pixel regions distributed in an array, a first wire region located between two adjacent rows of sub-pixel regions and a second wire region located between two adjacent columns of sub-pixel regions;

a gate line, located in the first wire region and extending along the first wire region;

a data line, located in the second wire region and extending along the second wire region, wherein the data line is provided with a support portion, and the support portion is located in in intersection region of the first wire region and the second wire region;

a sub-pixel unit, located in the sub-pixel region, wherein the sub-pixel unit comprises a pixel electrode, a common electrode and a thin film transistor; the thin film transistor is electrically connected with the gate line and is electrically connected with the data line; the pixel electrode is electrically connected with the thin film transistor, and an orthographic projection of the common electrode on the first substrate is overlapped with an orthographic projection of a corresponding gate line on the first substrate; and

a spacer, an orthographic projection of the spacer on the first substrate is located within an orthographic projection of the support portion on the first substrate,

wherein the liquid crystal layer comprises a negative liquid crystal,

wherein the first wire region is provided between each adjacent two rows of sub-pixel regions, and two gate lines are provided in each first wire region; two columns of the sub-pixel regions are provided between each adjacent two second wire regions, and one data line is provided in each second wire region;

in a row direction, a common electrode line extending in a column direction is provided between two sub-pixel regions between each adjacent two second wire regions, and the common electrode line is electrically connected with the common electrode.