| CPC G02B 6/4272 (2013.01) [G02B 6/4239 (2013.01); G02B 6/4243 (2013.01); G02B 6/4245 (2013.01); G02B 6/4283 (2013.01)] | 17 Claims |
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1. A method for manufacturing an optical interconnection module in which an optical fiber optical coupler is disposed at its lower portion using a Fan-Out Wafer-Level Packaging (FOWLP) process, the method comprising:
mounting an electronic chip on an electrical and thermal bench (ETB) disposed only in a first area on a temporary wafer on which an adhesive layer is formed;
mounting a photonics chip in a second area on the temporary wafer, wherein the second area is separated from the first area and is coplanar with the first area, and the photonics chip has a groove region formed on its bottom surface, facing a ReDistribution Layer (RDL), to allow the optical fiber optical coupler to be inserted into and placed in the groove region located at the lower portion of the optical interconnection module;
performing an epoxy molding compound (EMC) process on the electronic chip and the photonics chip mounted on the temporary wafer;
after removing the temporary wafer from the electronic chip and the photonics chip on which the EMC process has been performed and forming a dielectric layer in the removed region, forming the ReDistribution Layer (RDL) on the formed dielectric layer;
opening a side of the photonics chip on which the EMC process has been performed by performing dicing using the groove region formed in the photonics chip; and
connecting the optical fiber optical coupler to the open side of the photonics chip,
wherein the ETB has a concave shape for the electronic chip to be mounted therein, with a height of both sides of the ETB being a same as a height of the mounted electronic chip,
wherein regions of the RDL in contact with both sides of the ETB include metal patterns extending to pads, thereby providing an electrical ground for the electronic chip mounted on the ETB.
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