US 12,235,331 B2
Abnormality detection apparatus for resolver
Tatsuya Mori, Tokyo (JP); Hiroko Ikeda, Tokyo (JP); Kenji Ikeda, Tokyo (JP); Kenta Kubo, Tokyo (JP); and Toshihiro Matsunaga, Tokyo (JP)
Assigned to Mitsubishi Electric Corporation, Tokyo (JP)
Appl. No. 17/794,694
Filed by Mitsubishi Electric Corporation, Tokyo (JP)
PCT Filed Feb. 26, 2020, PCT No. PCT/JP2020/007582
§ 371(c)(1), (2) Date Jul. 22, 2022,
PCT Pub. No. WO2021/171391, PCT Pub. Date Sep. 2, 2021.
Prior Publication US 2023/0055461 A1, Feb. 23, 2023
Int. Cl. G01R 31/72 (2020.01); G01B 7/30 (2006.01)
CPC G01R 31/72 (2020.01) [G01B 7/30 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An abnormality detection apparatus for resolver comprising:
a resolver that is provided with a first system excitation winding, first system two output windings, a second system excitation winding, and second system two output windings;
a first system exciter configured to apply AC voltage of a first period to the first system excitation winding;
a second system exciter configured to apply the AC voltage of a second period different from the first period, to the second system excitation winding;+
a first system output signal detector configured to detect periodically output signals of the first system two output windings at preliminarily set detection timing;
a first system reduction processor configured to perform a second period component reduction processing which arithmetically reduces a value of a component of the second period, to detection values of the output signals of the first system two output windings;
a first system square sum calculator configured to calculate a first system square sum which is a sum of square values of the detection values of output signals of first system two output windings after the second period component reduction processing, based on values obtained by arithmetically reducing the value of the component of the second period from the detection values of the output signals of the first system two output windings; and
a first system abnormality detector configured to determine abnormality of first system, based on whether or not the first system square sum is within a preliminarily set normal range of first system,
wherein the second period is set longer than the first period,
wherein the first system reduction processor, as the second period component reduction processing, is further configured to add the detection values of output signals of first system two output windings detected at this time detection timing, and the detection values of output signals of first system two output windings detected at the detection timing earlier by a first system reduction processing interval than this time detection timing,
wherein when setting the second period to TB, the first system reduction processing interval is set to TB/2+TB×M (M is an integer greater than or equal to 0), and
wherein the first system square sum calculator is further configured to calculate the first system square sum which is a sum of square values of the detection values of output signals of first system two output windings after addition.