| CPC G01R 31/40 (2013.01) [G01K 7/22 (2013.01); G01R 15/04 (2013.01); G01R 19/16538 (2013.01); G01R 19/1659 (2013.01); H02H 3/20 (2013.01); H02H 5/04 (2013.01); H02M 3/33592 (2013.01)] | 10 Claims |

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1. A synchronous rectification circuit, comprising:
a multiplexer, including two input terminals and an output terminal;
a comparator, coupled to said output terminal of said multiplexer; and
a switch, including a control terminal coupled to said comparator;
wherein a first reference signal and a second reference signal are coupled to said two input terminals of said multiplexers; said multiplexer selectively outputs said first reference signal or said second reference signal to said comparator according to a comparison reference signal; and said comparator compares a detection signal of said switch according to said first reference signal or said second reference signal and generates a comparison result signal to said switch, and wherein said comparator compares said first reference signal with said detection signal; when said detection signal is smaller than said first reference signal, said comparison result signal controls said switch to turn on; said comparator compares said second reference signal with said detection signal; and when said detection signal is greater than said second reference signal, said comparison result signal controls said switch to cut off.
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