predetermining a first target surface roughness value and a second target surface roughness value associated with a first semiconductor substrate, wherein the second target surface roughness value is at least twice as large as the first target surface roughness value;

repeating a cycle of performing chemical vapor deposition (CVD) of a dielectric material to form a dielectric layer on a top surface of the first semiconductor substrate followed by chemical mechanical polishing (CMP) on the top surface of the first semiconductor substrate when a roughness of the top surface is larger than or equal to the second target surface roughness value; and

performing an additional CVD of the dielectric material on the top surface of the dielectric layer when the roughness of the top surface is smaller than the second target surface roughness value and larger than or equal to the first target surface roughness value.