CPC H10N 70/231 (2023.02) [H10B 63/24 (2023.02); H10B 63/84 (2023.02); H10N 70/021 (2023.02); H10N 70/8845 (2023.02)] | 20 Claims |
1. A method of forming at least one resistive memory array over a substrate, wherein each of the at least one resistive memory array is formed by:
forming an array of rail structures that extend along a first horizontal direction over the substrate, wherein each of the rail structures comprises a respective lower bit line and a respective upper bit line;
forming dielectric isolation structures extending along a second horizontal direction over the array of rail structures, wherein sidewalls of the rail structures are physically exposed to line trenches located between neighboring pairs of the dielectric isolation structures;
forming a layer stack of a resistive memory material layer and a selector material layer within each of the line trenches; and
forming a word line on each of the layer stacks within unfilled volumes of the line trenches, wherein:
lower bit lines comprise a first material selected from a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement and a conductive material other than the carbon-based conductive material; and
the upper bit lines comprise a second material that is different from the first material and selected from the carbon-based conductive material and the conductive material other than the carbon-based conductive material.
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