US 11,910,669 B2
Array substrate and display apparatus
Maoying Liao, Beijing (CN); Yang Zhou, Beijing (CN); Xin Zhang, Beijing (CN); and Huijuan Yang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/428,979
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Oct. 30, 2020, PCT No. PCT/CN2020/125180
§ 371(c)(1), (2) Date Aug. 6, 2021,
PCT Pub. No. WO2022/088021, PCT Pub. Date May 5, 2022.
Prior Publication US 2022/0352287 A1, Nov. 3, 2022
Int. Cl. H10K 59/40 (2023.01); G09G 3/3291 (2016.01); H10K 59/131 (2023.01); H10K 59/124 (2023.01); H10K 59/121 (2023.01); H01L 27/12 (2006.01); G09G 3/3258 (2016.01)
CPC H10K 59/131 (2023.02) [G09G 3/3258 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An array substrate, comprising a pixel driving circuit;
wherein the pixel driving circuit comprises a driving transistor; a first transistor; a second transistor; a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a storage capacitor;
wherein a gate electrode of the driving transistor is electrically connected to a first electrode of the third transistor, a second electrode of the first transistor, and a first capacitor electrode of the storage capacitor;
a first electrode of the driving transistor is electrically connected to a second electrode of the second transistor and a second electrode of the fourth transistor;
a second electrode of the driving transistor is electrically connected to a second electrode of the third transistor and a first electrode of the fifth transistor;
a second electrode of the fifth transistor is electrically connected to a second electrode of the sixth transistor; and
a first electrode of the fourth transistor is electrically connected to a second capacitor electrode of the storage capacitor;
wherein the array substrate comprises:
a base substrate;
a semiconductor material layer on the base substrate;
a gate insulating layer on a side of the semiconductor material layer away from the base substrate;
a plurality of gate lines respectively extending along a first direction and the first capacitor electrode of the storage capacitor on a side of the gate insulating layer away from the base substrate;
an insulating layer on a side of the plurality of gate lines away from the base substrate;
an interference preventing block and the second capacitor electrode on a side of the insulating layer away from the base substrate;
an inter-layer dielectric layer on a side of the interference preventing block and the second capacitor electrode away from the base substrate; and
a plurality of data lines respectively extending along a second direction, a plurality of voltage supply lines respectively extending along the second direction, a node connecting line on a side of the inter-layer dielectric layer away from the base substrate;
wherein the second capacitor electrode is electrically connected to a respective one of the plurality of voltage supply lines;
the node connecting line is connected to the first capacitor electrode through a first through hole, and connected to the first electrode of the third transistor through a second through hole; and
the respective one of the plurality of voltage supply lines is connected to the interference preventing block through a third through hole, the interference preventing block comprising a first arm and a second arm;
wherein in a plan view of a virtual line parallel to the first direction, the virtual line intersects with the node connecting line at a position of the second through hole; and wherein, along the first direction of the plan view of the virtual line, a first adjacent data line, the first arm, the node connecting line at the position of the second through hole, the second arm, and a second adjacent data line are sequentially arranged.