US 11,910,665 B2
Array substrate and display device
Pengfei Yu, Beijing (CN); Zhenhua Zhang, Beijing (CN); Shun Zhang, Beijing (CN); and Huijuan Yang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/270,883
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed May 7, 2020, PCT No. PCT/CN2020/089065
§ 371(c)(1), (2) Date Feb. 24, 2021,
PCT Pub. No. WO2021/223188, PCT Pub. Date Nov. 11, 2021.
Prior Publication US 2022/0123087 A1, Apr. 21, 2022
Int. Cl. G09G 3/3266 (2016.01); G09G 3/3275 (2016.01); H10K 59/131 (2023.01); H10K 71/00 (2023.01); G09G 3/3225 (2016.01); H10K 77/10 (2023.01); H10K 102/00 (2023.01)
CPC H10K 59/131 (2023.02) [G09G 3/3225 (2013.01); G09G 2310/0297 (2013.01); H10K 77/111 (2023.02); H10K 2102/311 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a base substrate comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a first peripheral area located on one side of the display area and a corner area adjacent to the first peripheral area;
a plurality of sub-pixels located at the display area;
a plurality of data lines located at the display area, electrically connected to the plurality of sub-pixels, and configured to provide a data signal to the plurality of sub-pixels;
a plurality of power lines located at the display area, electrically connected to the plurality of sub-pixels, and configured to provide a first power signal to the plurality of sub-pixels;
a plurality of control signal lines located at the first peripheral area and the corner area;
a plurality of data signal input lines located at the first peripheral area and the corner area;
a multiplexing circuit located at the first peripheral area and the corner area, located on one side of the plurality of control signal lines close to the display area, and comprising a plurality of multiplexing units, wherein at least one of the plurality of multiplexing units is electrically connected to the plurality of control signal lines, a data signal input line of the plurality of data signal input lines, and at least two of the plurality of data lines;
a first power bus located at the first peripheral area and the corner area, electrically connected to the plurality of power lines, and at least partially overlapping with the plurality of data signal input lines;
a plurality of control signal connecting lines at least partially overlapping with the plurality of data signal input lines, located between the first power bus and the display area, and electrically connected to the plurality of control signal lines; and
a plurality of control signal input lines at least partially overlapping with the first power bus, electrically connected to the plurality of control signal connecting lines and located on one side of the plurality of control signal connecting lines away from the display area.