CPC H10K 59/12 (2023.02) [G02B 27/0172 (2013.01); G06F 3/011 (2013.01); G09G 3/3225 (2013.01); H01L 27/1218 (2013.01); G02B 2027/0178 (2013.01); G09G 2310/0297 (2013.01); H10K 59/1201 (2023.02)] | 20 Claims |
1. A display system comprising:
a display element including a display active area disposed over a semiconductor backplane, wherein the display active area comprises a plurality of nodes above a minimum node size formed according to a first process node including a gate driver and a source driver integrated into the semiconductor backplane;
a discrete display driver integrated circuit (DDIC) that includes a display package with one or more control circuit elements, wherein the control circuit elements in the display package of the DDIC are formed separately from the semiconductor backplane, — and include a display serial interface configured to provide packet-based video data to the display element, as well as a timing controller configured to receive the packet-based video data, format the video data for input by the source driver, and generate control signals for the gate and source drivers, and wherein the DDIC comprises a plurality of nodes below a maximum node size that were formed according to a second, different process node; and
an interconnection component disposed between the display element and the discrete DDIC, wherein the interconnection component communicatively links the control circuit elements in the display package of the DDIC to the display element.
|