US 11,910,619 B2
Method for MRAM top electrode connection
Harry-Hak-Lay Chuang, Zhubei (TW); Hung Cho Wang, Taipei (TW); Sheng-Chang Chen, Hsinchu County (TW); and Sheng-Huang Huang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Mar. 24, 2022, as Appl. No. 17/703,065.
Application 17/703,065 is a continuation of application No. 16/884,353, filed on May 27, 2020, granted, now 11,322,543.
Prior Publication US 2022/0216268 A1, Jul. 7, 2022
Int. Cl. H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC H10B 61/22 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a memory device, comprising:
forming a first memory cell and a second memory cell over a substrate;
forming a sidewall spacer layer around the first and second memory cells;
forming a first dielectric layer over and around the first and second memory cells, wherein the first dielectric layer comprises sidewalls defining an opening spaced laterally between the first and second memory cells;
forming a second dielectric layer over the first dielectric layer, wherein the second dielectric layer is disposed in the opening;
performing a planarization process on the first and second dielectric layers, wherein at least a portion of the second dielectric layer is in the opening after the planarization process; and
performing an etching process on the first dielectric layer to form a plurality of upper openings over the first and second memory cells, wherein during the etching process the first dielectric layer is etched more quickly than the sidewall spacer layer.