US 11,910,617 B2
Ferroelectric memory device and method of forming the same
Chun-Chieh Lu, Taipei (TW); Han-Jong Chia, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); Bo-Feng Young, Taipei (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 16, 2020, as Appl. No. 17/098,919.
Claims priority of provisional application 63/031,040, filed on May 28, 2020.
Prior Publication US 2021/0375888 A1, Dec. 2, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 51/30 (2023.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 51/20 (2023.01)
CPC H10B 51/30 (2023.02) [H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); H10B 51/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of forming a ferroelectric memory device, comprising:
forming a multi-layer stack and comprising a plurality of dielectric layers and a plurality of conductive layers stacked alternately over a substrate, wherein sidewalls of the plurality of dielectric layers and the plurality of conductive layers define a trench penetrating therethrough;
selectively forming a plurality of ferroelectric portions discretely on the sidewalls of the plurality of conductive layers;
after forming the plurality of ferroelectric portions then forming a channel layer on the plurality of ferroelectric portions and the sidewalls of the plurality of dielectric layers; and
forming a conductive pillar along sidewalls of the channel layer.