US 11,910,612 B2
Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array
Tianhong Yan, Saratoga, CA (US); Scott Brad Herner, Portland, OR (US); Jie Zhou, San Jose, CA (US); Wu-Yi Henry Chien, San Jose, CA (US); and Eli Harari, Saratoga, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SunRise Memory Corporation, San Jose, CA (US)
Filed on Jun. 1, 2022, as Appl. No. 17/804,986.
Application 17/804,986 is a continuation of application No. 16/786,463, filed on Feb. 10, 2020, granted, now 11,398,492.
Claims priority of provisional application 62/947,405, filed on Dec. 12, 2019.
Claims priority of provisional application 62/804,080, filed on Feb. 11, 2019.
Prior Publication US 2022/0293623 A1, Sep. 15, 2022
Int. Cl. H10B 43/40 (2023.01); H01L 29/45 (2006.01); H01L 23/528 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/3205 (2006.01); H01L 21/225 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/40 (2023.02) [H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/2251 (2013.01); H01L 21/31111 (2013.01); H01L 21/32053 (2013.01); H01L 23/528 (2013.01); H01L 29/458 (2013.01); H01L 29/665 (2013.01); H01L 29/66742 (2013.01); H01L 29/78642 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A process for forming a transistor above a planar surface of a substrate, comprising:
Providing first and second conductive layers comprising each a material that is suitable for the first and the second conductive layers to form a drain region and a source region of the transistor, respectively, the first and second conductive layers being isolated from each other by an isolation layer;
providing an active layer in contact with both the first and second conductive layers, wherein the active layer comprises a material suitable for forming a channel region of the transistor and wherein a portion of the active layer is provided above either the first conductive layer or the second conductive layer;
providing a gate dielectric layer over the active layer;
providing a third conductive layer over gate dielectric layer;
etching the active layer, the gate dielectric layer and the third conductive layer to form a line structure around the second conductive layer, the isolation layer and the first conductive layer;
providing a passivation layer to enclose the third conductive layer, the gate dielectric layer, the first and the second conductive layers, the active layer, and the isolation layer;
etching the passivation layer to provide a via to expose a portion of the second conductive layer or a portion of the first conductive layer; and
providing a metallic layer on the exposed portion of second conductive layer or the exposed portion of the first conductive layer.