CPC H10B 43/27 (2023.02) [H01L 29/04 (2013.01); H01L 29/42344 (2013.01); H01L 29/7926 (2013.01); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
1. A three-dimensional semiconductor memory device, comprising:
a source structure on a substrate;
a stack including a plurality of gate electrodes, the plurality of gate electrodes stacked on the source structure;
a vertical channel portion penetrating the stack and the source structure, and the vertical channel portion being in contact with a side surface of the source structure;
a common source pattern in a trench penetrating the stack and the source structure; and
blocking patterns interposed between the source structure and the common source pattern in the trench, and the blocking patterns being spaced apart from each other,
wherein a distance between lower portions of the blocking patterns is larger than a distance between upper portions of the blocking patterns.
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