US 11,910,607 B2
Three-dimensional semiconductor devices
Jung-Hwan Kim, Seoul (KR); Sunggil Kim, Suwon-si (KR); Dongkyum Kim, Suwon-si (KR); Seulye Kim, Seoul (KR); and Ji-Hoon Choi, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 5, 2022, as Appl. No. 17/881,707.
Application 17/881,707 is a continuation of application No. 16/838,586, filed on Apr. 2, 2020, granted, now 11,424,264, issued on Aug. 23, 2022.
Claims priority of application No. 10-2019-0097697 (KR), filed on Aug. 9, 2019.
Prior Publication US 2022/0384482 A1, Dec. 1, 2022
Int. Cl. H01L 21/00 (2006.01); H10B 43/27 (2023.01); H01L 29/04 (2006.01); H01L 29/792 (2006.01); H01L 29/423 (2006.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 29/04 (2013.01); H01L 29/42344 (2013.01); H01L 29/7926 (2013.01); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional semiconductor memory device, comprising:
a source structure on a substrate;
a stack including a plurality of gate electrodes, the plurality of gate electrodes stacked on the source structure;
a vertical channel portion penetrating the stack and the source structure, and the vertical channel portion being in contact with a side surface of the source structure;
a common source pattern in a trench penetrating the stack and the source structure; and
blocking patterns interposed between the source structure and the common source pattern in the trench, and the blocking patterns being spaced apart from each other,
wherein a distance between lower portions of the blocking patterns is larger than a distance between upper portions of the blocking patterns.