CPC H04L 25/03057 (2013.01) | 20 Claims |
8. An integrated circuit, comprising:
a receiver circuit having a slicer and decision feedback equalization (DFE) circuitry, the DFE circuitry having a DFE coefficient, the slicer having a reference voltage; and
control circuitry configured to calibrate the DFE coefficient by:
measuring, at a first sample timing and by varying the DFE coefficient, a first eye height while receiving a first data pattern;
measuring, at the first sample timing by varying the DFE coefficient, a second eye height while receiving a second data pattern; and
based on the first eye height and the second eye height, adjusting the DFE coefficient to a first setting.
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