US 11,909,565 B2
Read eye training
Anirudha Shelke, Bengaluru (IN); Ashwin S. Madhavakaimal, Bangalore (IN); and Kiran Baby, Bangalore (IN)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Aug. 2, 2022, as Appl. No. 17/879,611.
Claims priority of provisional application 63/231,972, filed on Aug. 11, 2021.
Prior Publication US 2023/0048896 A1, Feb. 16, 2023
Int. Cl. H04L 25/03 (2006.01)
CPC H04L 25/03057 (2013.01) 20 Claims
OG exemplary drawing
 
8. An integrated circuit, comprising:
a receiver circuit having a slicer and decision feedback equalization (DFE) circuitry, the DFE circuitry having a DFE coefficient, the slicer having a reference voltage; and
control circuitry configured to calibrate the DFE coefficient by:
measuring, at a first sample timing and by varying the DFE coefficient, a first eye height while receiving a first data pattern;
measuring, at the first sample timing by varying the DFE coefficient, a second eye height while receiving a second data pattern; and
based on the first eye height and the second eye height, adjusting the DFE coefficient to a first setting.