US 11,909,405 B1
Digital coarse locking in digital phase-locked loops
Luigi Grimaldi, Villach (AT); Thomas Bauernfeind, Arbing (AT); Dmytro Cherniak, Villach (AT); Fabio Versolatto, Villach (AT); Andrew Wightwick, Ledenitzen (AT); Fabio Padovan, Villach (AT); and Giovanni Boi, Padua (IT)
Assigned to INFINEON TECHNOLOGIES AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Jan. 9, 2023, as Appl. No. 18/151,861.
Int. Cl. H03L 7/093 (2006.01); H03L 7/18 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/093 (2013.01) [H03L 7/099 (2013.01); H03L 7/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A digital phase-locked loop (DPLL) circuit comprising:
a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), wherein the first TDC is configured to, during an acquisition mode of the DPLL circuit, generate a phase error by:
receiving a reference clock signal from the reference clock source;
receiving a first clock signal that is based on an output of the DCO divided by a dividing factor;
computing a phase error using the reference clock signal and the first clock signal;
detecting cycle slipping in the computed phase error; and
in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on operation of the DPLL circuit; and
a first frequency divider circuit coupled to the DCO, wherein the first frequency divider circuit is configured to generate the first clock signal by dividing the output of the DCO by the dividing factor.