US 11,909,404 B1
Delay-locked loop offset calibration and correction
Andy Huei Chu, Saratoga, CA (US); Karthik Gopalakrishnan, Cupertino, CA (US); and Pradeep Jayaraman, San Jose, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 12, 2022, as Appl. No. 18/079,252.
Int. Cl. H03L 7/081 (2006.01); H03L 7/189 (2006.01); H03L 7/087 (2006.01)
CPC H03L 7/0818 (2013.01) [H03L 7/087 (2013.01); H03L 7/189 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for operating an interface circuit, comprising:
providing a master delay-locked loop (DLL) lock value indicating a delay adjustment made at a master DLL;
adjusting a delay of a slave DLL based on a master DLL code; and
temporarily enabling a replica phase detector at the slave DLL during an interface idle period, determining a slave DLL code, determining a configuration value based on the slave DLL code to the master DLL code, and then disabling the replica phase detector.