US 11,908,942 B2
Transistors having nanostructures
Cheng-Ting Chung, Hsinchu (TW); Ching-Wei Tsai, Hsinchu (TW); and Kuan-Lun Cheng, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTORMANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 7, 2022, as Appl. No. 17/860,022.
Application 17/860,022 is a continuation of application No. 17/023,125, filed on Sep. 16, 2020, granted, now 11,417,766.
Claims priority of provisional application 63/013,354, filed on Apr. 21, 2020.
Prior Publication US 2022/0352377 A1, Nov. 3, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/775 (2006.01); H01L 29/04 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01)
CPC H01L 29/7855 (2013.01) [H01L 21/823431 (2013.01); H01L 29/0673 (2013.01); H01L 29/1033 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66818 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01); H01L 29/045 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first transistor comprising:
first nanostructures disposed one over another and extending between a first source/drain feature and a second source/drain feature along a first direction, and
a first gate structure wrapping around each of the first nanostructures; and
a second transistor comprising:
second nanostructures disposed one over another and extending between a third source/drain feature and a fourth source/drain feature along the first direction, and
a second gate structure disposed over the second nanostructures,
wherein the first source/drain feature comprises a first width along a second direction perpendicular to the first direction,
wherein the third source/drain feature comprises a second width along the second direction,
wherein the first width is greater than the second width,
wherein the second gate structure comprises a gate dielectric layer and the gate dielectric layer disposed over two adjacent ones of the second nanostructures merge.