US 11,908,920 B2
Fin field-effect transistor device and method of forming the same
Shih-Yao Lin, New Taipei (TW); Kuei-Yu Kao, Hsinchu (TW); Chih-Han Lin, Hsinchu (TW); Ming-Ching Chang, Hsinchu (TW); and Chao-Cheng Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 18, 2022, as Appl. No. 17/722,787.
Application 17/722,787 is a division of application No. 16/822,609, filed on Mar. 18, 2020, granted, now 11,309,403.
Claims priority of provisional application 62/928,812, filed on Oct. 31, 2019.
Prior Publication US 2022/0238696 A1, Jul. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 21/306 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 21/30621 (2013.01); H01L 21/823431 (2013.01); H01L 29/66795 (2013.01); H01L 29/7856 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a fin protruding above a substrate;
isolation regions on opposing sides of the fin;
a gate structure over the fin, wherein the gate structure comprises a gate dielectric layer and a gate electrode over the gate dielectric layer;
gate spacers along opposing sidewalls of the gate structure, wherein a first width of a lower portion of the gate structure proximate to the isolation regions, measured between the gate spacers, decreases as the lower portion of the gate structure extends toward the isolation regions; and
a gate fill material along sidewalls of the lower portion of the gate structure, wherein the gate fill material is between the gate structure and the gate spacers, wherein the gate structure extends into the isolation regions, and is closer to the substrate than a lowest surface of the gate fill material facing the isolation regions.