US 11,908,919 B2
Multi-gate devices with multi-layer inner spacers and fabrication methods thereof
Chih-Ching Wang, Kinmen County (TW); Jon-Hsu Ho, New Taipei (TW); Wen-Hsing Hsieh, Hsinchu (TW); Kuan-Lun Cheng, Hsin-Chu (TW); Chung-Wei Wu, Hsin-Chu County (TW); and Zhiqiang Wu, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Mar. 12, 2021, as Appl. No. 17/200,291.
Claims priority of provisional application 63/031,314, filed on May 28, 2020.
Prior Publication US 2021/0376119 A1, Dec. 2, 2021
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66484 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 29/66553 (2013.01); H01L 29/66795 (2013.01); H01L 29/7831 (2013.01); H01L 29/7848 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatingly stacked;
forming a sacrificial gate structure over the fin structure;
etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space;
laterally etching the first semiconductor layers through the S/D space, thereby forming recesses;
forming a first insulating layer, in the recesses, on the etched first semiconductor layers;
after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and
after the second insulating layer is formed, forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer, and wherein the second insulating layer separates the first insulating layer from physically contacting the S/D epitaxial layer.